Semiconductor Device and Method of Manufacturing Thereof
This is a Continuation of International Application PCT/JP96/03369 with an international filing date of Nov. 15, 1996, now abandoned.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing thereof, and specifically to a semiconductor device having a semiconductor layer disposed on a substrate with an insulating layer therebetween, and a method of manufacturing the same.
2. Background Art
A so called SOI (Semiconductor on Insulator) structure is known as the one having a semiconductor layer placed on a substrate with an insulating layer therebetween in an attempt to reduce the junction capacitance, to improve the breakdown voltage for isolating elements from each other, or to prevent the turn on or latch up of a parasitic thyristor. An MOSFET (Metal Oxide Semiconductor Field Effect Transistor) formed at the semiconductor layer of the structure is generally referred to as SOI-MOSFET.
As shown in FIG. 32, the SOI-MOSFET is built at a semiconductor layer (hereinafter referred to as SOI layer) 105 deposited on a substrate 1 with an insulating layers 3 therebetween. Specifically, the SOI-MOSFET is constituted of a drain region 105a and a source region 105b formed at SOI layer 105, and a gate electrode layer 109 placed on a region 105c (hereinafter referred to as channel formation region) between drain region 105a and source region 105b and opposite to channel formation region 105c with a gate insulating layer 7 therebetween.
Drain region 105a and source region 105b of the SOI-MOSFET conventionally have a low breakdown voltage since the potential of SOI layer 105 (hereinafter conveniently referred to as body potential) is floating.
More specifically, in the case of n channel, when voltage is applied to gate electrode layer 109 to form a channel at the surface of channel formation region 105c, electrons move from source region 105b toward drain region 105a. Impact ionization caused by the electrons generates a number of electron-hole pairs in the vicinity of the edge of drain region 105a. Although the electrons are removed from drain region 105a to the outside of SOI layer 105, the holes accumulate in SOI layer 105 because of the floating state of SOI layer 105.
Consequently, when a positive voltage is applied to SOI layer 105, source/drain regions 105a and 105b and channel formation region 105c are forward biased. Accordingly, current easily flows between drain region 105a and source region 105b and source drain breakdown voltage decreases.
A proposed element isolation method for improving the source-drain breakdown voltage is field shield isolation (hereinafter referred to as FS isolation).
FIG. 33 is a bird""s eye view illustrating a structure of an SOI-MOSFET to which the FS isolation structure is applied. FIG. 34A is a schematic plan view of the MOSFET portion viewed in the direction of the arrow H of FIG. 33, and FIG. 34B is a schematic plan view along the Fxe2x80x94F line of FIG. 34A.
Referring chiefly to FIG. 33, an SOI layer 105 is formed on a silicon substrate 1 with a buried insulating layer 3 interposed. As described in relation to FIG. 32, an MOSFET constituted of source/drain regions 105a, 105b and a gate electrode layer 109 is formed at SOI layer 105.
Gate electrode layer 109 extends in a region opposite to SOI layer 105 with a gate insulating layer 7 therebetween while keeping a prescribed gate length (FIG. 34A).
The FS isolation structure is formed to have an FS plate 11 opposite to SOI layer 105 at an edge of the region where the MOSFET is formed with an intervening insulating layer. According to the method of isolating transistors by the FS isolation method, the potential of SOI layer 105 under FS plate 11 is fixed by applying a prescribed voltage to FS plate 11 for electrically isolating devices such as transistors that are adjacent to each other.
The voltage applied to FS plate 11 is, for example, 0V for an nMOSFET, and Vcc (Power supply voltage) for a pMOSFET.
A body contact 23 for drawing out potential from SOI layer 105 is provided opposite to the MOSFET formation region with SOI layer 105 under FS plate therebetween.
By providing body contact 23 on the opposite side of the MOSFET formation region with the FS isolation therebetween, holes generated by the impact ionization can be drawn out from the body contact while electrical isolation between edges of the source and the drain of adjacent transistors is maintained. The source-drain breakdown voltage can be improved since holes in SOI layer 105 can be drawn out.
However, if the body potential is fixed by providing body contact 23 (body fix), an advantage specific to the SOI-MOSFET of a small substrate bias effect is lost. Further, a problem arises that an advantage of the SOI structure of high speed and low power consumption is decreased. The problem is hereinafter described in detail.
FIG. 35 is a cross sectional view schematically showing a structure of a transistor formed at a normal semiconductor substrate (hereinafter referred to as bulk-transistor). Referring to FIG. 35, the bulk-transistor includes a drain region 205a and a source region 205b formed to define a channel region 205e at a semiconductor substrate 201, and a gate electrode layer 209 formed on the region therebetween with an intervening gate insulating layer 207.
The substrate bias effect described above refers to increase in threshold voltage Vth caused by a depletion layer 205d extending toward substrate 201 when a junction of source/drain regions 205a and 205b and substrate 201 is reverse biased. If the channel length of the bulk transistor is long, threshold voltage Vth increases according to the equation below.       V    ⁢          xe2x80x83        ⁢    t    ⁢          xe2x80x83        ⁢    h    =            V      FB        +          2      ⁢              xe2x80x83            ⁢              φ        F              +                            2          ⁢                      xe2x80x83                    ⁢                      ϵ            S                    ⁢                      ϵ            O                    ⁢          q          ⁢                      xe2x80x83                    ⁢                                    N              A                        ⁡                          (                                                2                  ⁢                                      xe2x80x83                                    ⁢                                      φ                    F                                                  +                                  V                  B                                            )                                                  C        ox            
VFB: flat band voltage
xcfx86F: built-in potential of channel 205e 
xcex5O: dielectric constant in vacuum
xcex5S: relative dielectric of silicon
q: a charge amount
NA: concentration of impurities in channel 205e
COX: gate capacitance
Variation of threshold voltage Vth of the bulk-transistor according to substrate bias VB is shown in FIG. 36.
If the MOSFET is formed at a floating SOI layer 105 shown in FIG. 37, substrate bias VB is applied to SOI layer 105 via a buried oxide film 3. Therefore, substrate bias VB has little effect on threshold voltage Vth. As shown in FIG. 38, threshold voltage Vth scarcely changes with substrate bias VB.
However, if substrate bias VB is directly applied to SOI layer 105 as shown in FIG. 39 to fix the body, the junction is reverse biased when substrate bias VB is applied as in the bulk-transistor, resulting in increase in threshold voltage Vth due to a depletion layer 105d extending into a channel formation region 105c even in the SOI-MOSFET.
If threshold voltage Vth increases as described above, drain current Id decreases to make it difficult to operate an LSI (Large Scale Integrated Circuit) at a high speed.
In addition, the high threshold voltage Vth prevents reduction of supply voltage, and power consumption increases.
One object of the present invention is to provide a semiconductor device having an excellent source-drain breakdown voltage as well as a small substrate bias effect operating at high speed and with low power consumption, and a method of manufacturing such a semiconductor device.
A semiconductor device according to the present invention includes a semiconductor layer, a gate insulation type field effect transistor, and a conductive layer for isolation. The semiconductor layer is disposed on a substrate with an insulating layer therebetween. The gate insulation type field effect transistor includes a pair of source/drain regions arranged at the semiconductor layer spaced from each other, and a gate electrode layer opposite to a channel formation region between the paired source/drain regions with a gate insulating layer therebetween. A channel is formed in the channel formation region by controlling the potential of the gate electrode layer. The conductive layer for isolation is electrically insulated from the semiconductor layer. The gate insulation type field effect transistor is electrically isolated from other elements by controlling the potential of the isolation conductive layer to fix the potential of a region of the semiconductor layer opposite to the insulation conductive layer. Potential can be applied to the channel formation region from a prescribed region via the region of the semiconductor layer opposite to the isolation conductive layer. In the channel formation region, edge portions on both sides of the channel formation region and a central portion sandwiched between the edge portions are placed in the direction of the channel width. A region of the semiconductor layer, located between the central portion and the prescribed region and opposite to the gate electrode layer (opposite region), has a structure which is completely depleted prior to the central portion when voltage is applied to the prescribed region.
The semiconductor device of the present invention is structured such that a region at the edge of the channel formation region is completely depleted before the central portion thereof is depleted when voltage is applied to the gate. If the region at the edge is completely depleted prior to depletion of the central portion, subsequent application of the body potential to the central portion is blocked. Accordingly, extension of a depletion layer at the junction of the source/drain regions and the semiconductor layer in the central portion is prevented, so that threshold voltage Vth can be reduced. Since threshold voltage Vth decreases, drain current Id increases to easily implement high speed operation of the LSI. Further, reduction of threshold voltage Vth provides a reduced supply voltage and thus a reduced power consumption.
Before the edge portion is completely depleted, carriers (hole or electron) generated by impact ionization are drawn out from the semiconductor layer through a body contact. As a result, the number of carriers accumulating in the central portion after the edge portion is completely depleted can be reduced compared with a semiconductor layer which is completely floating. Therefore, reduction of source-drain breakdown voltage due to accumulation of carriers in the semiconductor layer can be prevented. After the edge portion is completely depleted, carriers are drawn out from the central portion to some extent by diffusion or recombination. As such, reduction of source-drain breakdown voltage can be prevented compared with the completely floating semiconductor layer.
In the aspect described above, the opposite region is preferably located at the edge portion of the channel formation region.
Further, in the above described aspect, an area of a cross section of the channel formation region in the direction of the channel length defined by (sandwiched between) the front and back surfaces of the semiconductor layer is preferably smaller at the edge portion than at the central portion.
By making the cross sectional area of the edge portion different from that of the central portion, the edge portion can be completely depleted prior to depletion of the central portion. As a result, a gate insulation type field effect transistor which is superior in the source-drain breakdown voltage, has a small substrate bias effect, and operates at high speed with low power consumption can be obtained.
In the aspect described above, a channel length at the edge portion of the channel formation region is preferably smaller than a channel length at the central portion of the channel formation region.
Since widths of the edge portion and the central portion in the direction of the channel length are different from each other, the edge portion can be completely depleted prior to depletion of the central portion. Consequently, a gate insulation type field effect transistor which is superior in the source-drain breakdown voltage, has a small substrate bias effect, and operates at high speed with low power consumption can be obtained.
In the aspect described above, a gate length of the gate electrode layer is preferably smaller at a location opposite to the edge portion than at a location opposite to the central portion.
The edge portion and the central portion different from each other in the width in the direction of the channel length can be easily formed by injecting impurities into the semiconductor layer with the gate electrode as a mask.
In the above described aspect, preferably, the edge portion has a region where a thickness of the semiconductor layer is smaller than that at the central portion.
By providing different thicknesses of the semiconductor layer to the edge portion and the central portion, the edge portion can be completely depleted prior to depletion of the central portion. As a result, a gate insulation type field effect transistor having a superior source-drain breakdown voltage and a small substrate bias effect, and operating at high speed with low power consumption can be obtained.
In the aspect described above, at the edge portion, a trench having a depth of at least 100 xc3x85 is formed at the front or back surface of the semiconductor layer.
If the depth of the trench is less than 100 xc3x85, the effect of the complete depletion of the edge portion preceding the central portion cannot be sufficiently achieved.
In the above described aspect, the source/drain region has a first impurity region of a relatively high concentration and a second impurity region of a relatively low concentration adjacent to the first impurity region on the channel formation region side. Preferably, the width in the channel length direction of the second impurity region adjacent to the edge portion is larger than that of the second impurity region adjacent to the central portion.
The second impurity region has a width larger at the edge portion than at the central portion. The second impurity region has a high parasitic resistance since the concentration of the impurities therein is relatively small. Therefore, when the transistor is turned on, current chiefly flows in the central portion having a narrow width of the second impurity region and a low parasitic resistance. In other words, the current hardly flows in the edge portion having a narrow width in the channel length direction, and an insulation gate type field effect transistor which is immuned to the short channel effect can be obtained.
In the aspect described above, a reflection film having a shape which is matched to that of the gate electrode layer is preferably formed on the gate electrode layer.
Since the reflection film is provided on the gate electrode layer, a resist region corresponding to the top of the edge portion can be exposed excessively by irregular reflection of exposure light from the reflection film when the gate electrode layer is exposed for patterning thereof Accordingly, the gate electrode layer having its length smaller at the edge portion than at the central portion can be formed without changing a gate electrode pattern of a photomask, and the manufacturing process can be simplified.
In the aspect described above, the semiconductor layer has an extended region which is electrically connected to the channel formation region and extends to the prescribed region with its circumference insulated. Potential is applicable to the extended region from the prescribed region, and the conductive layer for isolation is opposite to the extended region. The opposite region is located in the extension region between the prescribed region and a region opposite to the isolation conductive layer.
As a result, a region which is completely depleted prior to depletion of the central portion can be placed outside the region where the gate insulation type field effect transistor is formed.
In the above described aspect, preferably the concentration of the impurities in the opposite region is lower than that in the channel formation region.
Since the concentration of impurities in the opposite region and that in a region sandwiched between the paired source/drain regions are different from each other, the opposite region can be completely depleted prior to the region sandwiched between the paired source/drain regions. Consequently, an insulation gate type field effect transistor having a superior source-drain breakdown voltage and a small substrate bias effect, and operating at high speed and with low power consumption can be obtained.
In the aspect described above, the gate electrode layer preferably covers the surface of the top of the opposite region and both sides of the region.
Since the depletion layer can extend from the surface of the opposite region and both sides thereof, the opposite region can be completely depleted speedily. As a result, the effect of the substrate bias can be reduced.
A method of manufacturing a semiconductor device having a structure with a semiconductor layer formed on a substrate with an insulating layer interposed therebetween according to the present invention including the following steps.
A conductive layer for isolation electrically insulated from the semiconductor layer is next formed. A gate electrode layer opposite to the semiconductor layer with a gate insulating layer therebetween is formed. Paired source/drain regions are formed spaced from each other by introducing impurities into the semiconductor layer using the gate electrode layer as a mask. A gate insulation type field effect transistor formed of the paired source/drain regions and the gate electrode layer is fabricated, where a channel is formed in a channel formation region sandwiched between the paired source/drain regions by controlling the potential of the gate electrode layer. The gate insulation type field effect transistor can be electrically isolated from other elements by controlling the potential of the conductive layer for isolation to fix the potential of a region of the semiconductor layer opposite to the conductive layer for insulation. The channel formation region is provided such that potential can be applied from a prescribed region thereto via the region of the semiconductor layer opposite to the isolation conductive layer. In the channel formation region, two edge portions located on both sides and a central portion sandwiched between the edge portions are arranged in the direction of the channel width. The gate electrode layer is formed to have a region of a gate length smaller on the edge portions than on the central portion.
The edge portions and the central portion having different widths in the channel length direction can be easily formed by injecting impurities into the semiconductor layer using the gate electrode as a mask.
In the aspect described above, the step of forming the gate electrode layer includes a step of exposing a photoresist applied to a conductive layer with exposure light transmitted through a photomask having a gate electrode pattern, followed by developing to form a resist pattern and etching of the conductive layer using the resist pattern as a mask. At a location corresponding to an edge portion of the gate electrode pattern, there is a gap having a width smaller than the limit of resolution of a conventional stepper and isolating the gate electrode pattern.
As a result, there is a wider selection of shapes of the gate electrode pattern of the photomask.
In the above described aspect, in the step of forming the gate electrode layer, the conductive layer is patterned by the photolithography with a reflection film formed on the conductive layer corresponding to the gate electrode layer.
Since the reflection film is formed on the gate electrode layer, a resist region corresponding to the top of the edge portion can be exposed excessively by irregular reflection of exposure light from the reflection film when the gate electrode layer is exposed for patterning. Therefore, the gate electrode layer having its length smaller at the edge portions than at the central portion can be obtained without changing the shape of the gate electrode pattern of the photomask, and the manufacturing process can be simplified.
In the aspect described above, a step is further provided by which an insulating layer is formed to cover the gate electrode layer, and the insulating layer is left at a sidewall of the gate electrode layer by anisotropically etching the insulating layer. The region of the gate electrode layer having a small gate length located on the edge portion is provided to have a prescribed width in the direction of the gate width. The thickness of the insulating layer when it is formed is at least two times larger than the prescribed width.
Accordingly, an insulation gate type field effect transistor having its edge portion which is immuned to the short channel effect can be obtained.
In the aspect described above, the step of forming the gate electrode layer includes a step of exposing a photoresist applied onto the conductive layer with exposure light transmitted through a photomask having a gate electrode pattern, forming a resist pattern through development, and etching the conductive layer using the resist pattern as a mask. A first line width located correspondingly to the edge portion of the gate electrode pattern is smaller than a second line width located correspondingly to the central portion of the gate electrode pattern. A line width located correspondingly to a region sandwiched between the edge portion and the central portion of the gate electrode pattern is larger than the second line width.
Accordingly, a gate insulation type field effect transistor having its edge portion immune to the short channel effect can be obtained.